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-- Company: 
-- Engineer:
--
-- Create Date:   09:33:13 05/27/2010
-- Design Name:   ProcesseurEtRom
-- Module Name:   /nfs/ensibull/telesun/lelubrec/Processeur/test_pin.vhd
-- Project Name:  Processeur
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: ProcesseurEtRom
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_pin_vhd IS
END test_pin_vhd;

ARCHITECTURE behavior OF test_pin_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT ProcesseurEtRom
	PORT(
		CLK : IN std_logic;
		RESET : IN std_logic;
		PIN : IN std_logic_vector(7 downto 0);          
		POUT : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL CLK :  std_logic := '0';
	SIGNAL RESET :  std_logic := '0';
	SIGNAL PIN :  std_logic_vector(7 downto 0) := (others=>'0');

	--Outputs
	SIGNAL POUT :  std_logic_vector(7 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: ProcesseurEtRom PORT MAP(
		CLK => CLK,
		RESET => RESET,
		PIN => PIN,
		POUT => POUT
	);
	
   RESET <= '1', '0' after 431 ns;
	
   process 
   begin
		CLK<='1';
		wait for 10 ns;
		CLK<='0';
		wait for 10 ns;
	end process;

  
	tb : PROCESS
	BEGIN
	   PIN <= "00000100";
		while true loop
			wait until rising_edge(clk);
			PIN <= "00000100";
	end loop;
	END PROCESS;

END;
